News / Articles |
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TSMC Names Time to Market Design Center Alliance Member
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August 19th, 2008 |
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TTM’s Ability to Take Design from Concept to Silicon Lauded
SAN JOSE , CALIF. , August 19, 2008
Time to Market Inc. (TTM) today was named a TSMC Design Center Alliance (DCA) Program Partner . TSMC DCA Program is one of the key collaborative components of the company’s recently unveiled Open Innovation Platform™. Open Innovation Platform™ is a platform for innovations, hosted by TSMC and open to TSMC customers and partners. It is built on TSMC’s design-enabling building blocks and an ecosystem interface.
TTM employs Cadence ® Design Systems’ Encounter ® Digital IC Design Platform for 65nm designs and below. It recently designed and validated a networking system on chip (SoC) in record time using Cadence’s Litho Physical Analyzer for layout printability checking and using SoC Encounter GXL, which includes both NanoRoute and Cadence Chip Optimizer for correction. TSMC cited TTM’s ability to offer a cost-effective, reliable and dependable path for taking a design from concept to silicon. “Our mission to build a seamless interface for our customers , along with our varied experience complements the high standards set by TSMC,” remarks Venkata Simhadri, TTM’s president and chief executive officer. |
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TTM, Inc. adopts Cadence Holistic DFM Solutions for 65nm and Below Designs
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April 22nd, 2008 |
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Cadence SoC Encounter and Litho Physical Analyzer Optimize Yields and Improve Manufacturability
SAN JOSE, Calif., April 22, 2008
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced that Time To Market, Inc. (TTM), a leading ASIC design house, was able to detect hot spots and optimize yields for a complex 65-nanometer design using a holistic design-for-manufacturability flow from Cadence that includes the Cadence® SoC Encounter™ XL system and the Cadence Litho Physical Analyzer. The proof-point project provided TTM with state-of-the-art DFM experience and allowed the company to move to Cadence model-based DFM solutions for ongoing 65-nanometer and below designs.
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Sagantec and Time To Market team up
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November 19th, 2007 |
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Sagantec and Time To Market team up to offer design migration solutions
Collaboration enables access to alternate and new process technologies
Fremont, Calif., Nov. 19, 2007 - Sagantec and Time To Market Inc. (TTM) of San Jose, CA, today announced a collaboration to jointly deliver complete integrated circuit (IC) design migration solutions. This program offers a variety of unique strategies for re-implementation of existing designs to new process technologies... |
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TTM - Expanding in India
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January 7th, 2005 |
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TTM Will become its third design center, after California and Hyderabad and plans to increase headcount in India to 60 in 3 months. |
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TTM - Year End News Letter
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January 1st, 2004 |
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TTM completes one more year in business, and with this it's been five years of successful growth and execution for us. |
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Cadence Design Systems
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September 24, 2003 |
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New Cadence Encounter Version 3.2 Reduces Chip Development Time. TTM's expert team of designers relies on Cadence's proven Encounter platform to deliver production silicon. |
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Chartered Expands Design Services Alliance Program
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March 26, 2003 |
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TTM provides a very cost effective and risk free route for COT customers, fabricating their ASICS with the leading semiconductor fabs and using IP from different vendors. |
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TTM / TriCN Announcement
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December 17, 2002 |
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TTM Signed a strategic partnership with "TriCN" a semiconductor IP Company. Step towards TTM's Efforts to provide a turnkey ASIC Solution to Customers. |
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TTM's success story
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April 07, 2002 |
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| TTM Tapes out the Largest Chip at Agere Systems and has First-Time Success with Silicon |
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Time To Market Inc. enters into Design Service Agreement with UMC.
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Grant of Leading Edge Design Software to Custom Engineering Program Continues Avant!'s Worldwide Support of Educational Development. |
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