Hyderabad, India.
Physical Design Lead
Strong hands-on experience on working with multi-million designs in 0.13um and 90nm technologies and lower in the areas of logic synthesis, low power synthesis, basic understanding of timing constraints, knowledge in DFT, place and route, clock tree synthesis, parasitic extraction, timing closure, timing analysis using primetime/PKS, IR-drop analysis, physical verification using Calibre. Should be able to understand the Physical Design flow, maintain it and lead a team of 3-4 physical design engineers. Should be strong in TCL/TK or PERL
For place&route, timing closure, experience in Cadence's SoC Encounter is an advantage.
Embedded Software Engineers Position Description
1. 3 to 7 years of experience in Device drivers development on any RTOS.
2. Should have hands on experience in embedded systems.
3. Knowledge on networking protocols and Multimedia technology is desirable.
4. Experience in Low level assembly programming required [ 8051, ARM, MIPS ]
5. Excellent C/C++ programming skills.
6. Should have the ability to work independently, be self motivated and proactive.
7. Excellent attitude to work in teams and good communications skills are required.
Location: Hyderabad/Bangalore/USA
Emails: giri@time2mkt.com
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